Field of the Invention
The present invention relates to a method for fabricating a semiconductor component having at least one transistor cell and an edge cell arranged adjacent to the transistor cell.
It is sufficiently known for power MOSFETs to be constructed in a cellular fashion. That is to say, to provide a multiplicity of transistor structures arranged next to one another, which in each case form a transistor. These transistors are connected in parallel to outwardly form the power MOSFET, whose current-carrying capacity substantially depends on the number of transistor structures connected in parallel. The cellular construction of a vertical power MOSFET is described, for example, in Stengl/Tihanyi: xe2x80x9cLeistungs-MOSFET-Praxisxe2x80x9d [xe2x80x9cpower MOSFETs in practicexe2x80x9d], Pflaum Verlag, Munich, 1992, pages 33, 34.
An n-conducting power MOSFET has an n-doped semiconductor body into which, proceeding from a front side, p-doped channel zones are introduced. In turn, n-doped source zones are formed in the p-doped channel zones. The rear side of the semiconductor body usually forms the drain zone of the transistor. The semiconductor body usually has a heavily doped semiconductor substrate and a more weakly doped epitaxial layer in which the channel zones are formed and which forms the drift path of the components. A gate electrode is formed in a manner insulated from the semiconductor body. This gate electrode runs adjacent to the source zone, the channel zone and the drift zone. The doping of the abovementioned zones is complementary to the abovementioned dopings in the case of a p-conducting MOSFET.
The sequence of the source zone, the channel zone doped complementary with respect to the source zone and the drift zone doped complementary with respect to the channel zone results in the formation of a parasitic bipolar transistor which, in the case of an n-conducting MOSFET, is an npn bipolar transistor whose base is formed by the channel zone. If, during the operation of the component, p-type charge carriers (holes) reach, for example, in the event of breakdown or commutation, into the channel zone, often also referred to as body zone, then a voltage drop may arise in the channel zone and drive the parasitic bipolar transistor.
The driven parasitic bipolar transistor emits n-type charge carriers (electrons). These electrons inevitably pass into regions with a high field strength, where they bring about, via impact ionization, charge carrier multiplication and thus a second breakdown (second breakthrough). P-type charge carriers (holes) produced as a result of this are conducted into the channel zone. That is to say, into the base of the parasitic bipolar transistor, and thereby amplify the bipolar effect. This process starts to escalate in an uncontrolled manner, and the component is ultimately destroyed.
Edge cells, that is to say, transistor cells at the edge of the transistor cell array, are especially affected by this phenomenon since, for the edge cells, the entire edge substructure acts as an entry region for charge carriers. All holes formed in the edge region traverse the edge cells, resulting in a high voltage drop in the p-doped channel zone. Voltage breakdowns of the field-effect transistor thus occur in an amplified fashion in the region of the edges of the cell array. In order to prevent this, or in order to bring the dielectric strength in the edge region at least to the value of the dielectric strength of transistor cells in the center of the cell array, it is known for the edge cells to be formed differently than the rest of the transistor cells. The essential difference between the edge cells and the transistor cells is that the edge cells have no source zone, so that, rather than a parasitic bipolar transistor, merely a diode is formed by the edge cells, in which case, in the case of an n-conducting MOSFET, a p-doped region of the edge cell, which corresponds to the channel zone in the case of the transistor cells, forms the anode of the diode.
In customary methods for fabricating such vertical power MOSFETS, first a semiconductor body of a specific conduction type (n-conducting in the case of an n-conducting MOSFET) is provided, and channel zones of a complementary conduction type are subsequently introduced into the semiconductor body in a manner proceeding from the front side. In order to form the later gate electrode, first an insulation layer, usually a semiconductor oxide, is deposited onto the semiconductor body, and an electrode layer is subsequently applied to the insulation layer. Cutouts are subsequently produced above the channel zones in the insulation layer and the electrode layer, and the channel zones are subjected to doping reversal in the regions uncovered by virtue of the cutouts in order to form the source zones. A further insulation layer is subsequently deposited onto this configuration, and cutouts are produced in the insulation layer above the channel zones or the source zones in order to make contact with the source zones. In this case, the further insulation layer serves for insulation between the gate electrodes and a source electrode that makes contact with the source zones. In this case, the source electrode is also intended to make contact with the channel zone or anode zone of the edge cells, so that contact holes likewise have to be produced there in the further insulation layer. In order to prevent source zones from being fabricated in the region of the edge cells, the known fabrication method requires an additional method step which follows the fabrication of the cutout in the insulation layer applied to the semiconductor body and the electrode layer. During this method step, a protective layer, for example, a photoresist, is deposited in the region of the edge cells, which covers the surface regions of the semiconductor body that are uncovered in the contact holes, in order thus to prevent a doping reversal.
It is accordingly an object of the invention to provide a method for fabricating a semiconductor component having at least one transistor cell and an edge cell configured adjacent to the transistor cell, which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
In particular, it is an object of the invention to provide a method for fabricating a semiconductor component having at least one transistor cell and an edge cell arranged adjacent to the transistor cell in which an additional method step for preventing a doping in the region of the edge cell can be dispensed with.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a semiconductor component. The method includes steps of:
providing a semiconductor body having a front side, a rear side, at least one transistor cell with at least one channel zone extending into the semiconductor body from the front side, at least one edge cell having at least one first terminal zone configured at a distance from the channel zone, an insulation layer applied to the front side of the semiconductor body, an electrode layer applied to the insulation layer, a cutout formed above the channel zone in the insulation layer and in the electrode layer, and a cutout formed above first terminal zone in the insulation layer and in the electrode layer, the channel zone and the first terminal zone being doped by the same conduction type, which is complementary with respect to surrounding regions of the semiconductor body, the edge cell being adjacent the transistor cell, and the first terminal zone extending into the semiconductor body from the front side;
doping a region of the channel zone that is uncovered by the cutout formed above the channel zone with a dopant of a complementary conduction type with respect to the channel zone to form a first complementary doped region, and doping a region of the first terminal zone that is uncovered by the cutout formed above the first terminal zone with a dopant of a complementary conduction type with respect to the first terminal zone to form a second complementary doped region;
depositing a further insulation layer and patterning the insulation layer to produce a first cutout above the channel zone and to produce a second cutout above the first terminal zone, the electrode layer in the channel zone remaining covered by the insulation layer, the second cutout exposing the cutout formed above the first terminal zone in the electrode layer and in the insulation layer; and
fabricating a first contact hole at a bottom of the first cutout of the further insulation layer, the first contact hole reaching through the first complementary doped region into the channel zone, and fabricating a second contact hole above the first terminal zone to at least approximately remove the second complementary doped region.
The semiconductor body preferably includes a heavily doped semiconductor substrate to which a more weakly doped epitaxial layer is applied, in which the channel zone and the first terminal zone are formed. The channel zone and the first terminal zone do not necessarily differ structurally at this juncture of the method, the different designations are chosen in order to provide a better understanding with regard to their later function.
In accordance with an added feature of the invention, a doping is performed using the electrode layer as a mask to introduce the channel zone and the first terminal zone into the semiconductor body.
In accordance with an additional feature of the invention, before applying the insulation layer and the electrode layer to the front side of the semiconductor body, a doping is performed to introduce the channel zone and the first terminal zone into the semiconductor body.
In accordance with another feature of the invention, the method includes subdividing the electrode layer into at least one first section in a region of the transistor cell and a second section in a region of the edge cell.
In accordance with a further feature of the invention, the method includes performing the step of subdividing the electrode layer by fabricating a cutout reaching at least as far as the insulation layer.
In accordance with a further added feature of the invention, the method includes performing an ion implantation to fabricate the first complementary doped region and the second complementary doped region.
In accordance with a further additional feature of the invention, the method includes doping the semiconductor body complementary with respect to the channel zone and the first terminal zone.
In accordance with another added feature of the invention, the method includes providing the insulation layer as a semiconductor oxide.
In accordance with another additional feature of the invention, the first electrode layer includes a metal or a heavily doped semiconductor material.
In accordance with yet an added feature of the invention, first electrode layer includes polysilicon.
In accordance with yet an additional feature of the invention, the method includes providing the semiconductor body with a heavily doped semiconductor substrate and applying an epitaxial layer to the semiconductor substrate.
In accordance with yet another feature of the invention, the method includes doping the semiconductor substrate more heavily than the epitaxial layer.
The inventive method for fabricating a semiconductor component having at least one transistor cell and an edge cell arranged adjacent to the transistor cell provides the method steps explained below.
The channel zone and the first terminal zone can be fabricated in the semiconductor body using conventional methods with mask techniques. These zones are preferably produced by diffusion methods and/or ion implantation methods. In this case, the channel zone and the first terminal zone may be produced in the semiconductor body even before the insulation layer produced, for example, by performing an oxidation, and the electrode layer are applied to the front side of the semiconductor body. The cutouts are then produced above the channel zone and first terminal zone that are already present in the semiconductor body.
The channel zone and the first terminal zone may also be produced after the application of the first insulation layer and the electrode layer and the fabrication of the cutouts above the channel zone and the first terminal zone. The electrode layer then serves as a mask. In this case, the doping is preferably effected by performing an implantation method and a subsequent diffusion method. The diffusion method causes the dopants to propagate under the edges of the mask.
Afterward, regions of the channel zone and of the first terminal zone which are uncovered in the cutouts of the electrode layer and the insulation layer are doped with dopants of a complementary conduction type with respect to the channel zone and the first terminal zone. The region doped complementary with respect to the channel zone forms the later source zone of the transistor cell. In this case, the epitaxial layer forms the drift zone of all the transistor cells and the semiconductor substrate forms the drain zone of all the transistor cells.
In a next method step, a further insulation layer is deposited onto the configuration with the patterned electrode layer and the pattered insulation layer applied to the semiconductor body. The further insulation layer is patterned in such a way that a first cutout is produced above the channel zone of the transistor cells. The electrode layer in this region remains covered by the further electrode layer. The patterning of the further insulation layer also includes the fabrication of a second cutout above the first terminal zone of the edge cell. The second cutout is produced in such a way that the cutout in the electrode layer and the insulation layer applied to the semiconductor body is uncovered.
Afterward, for example by using an etching method, a contact hole is produced in the semiconductor body above the channel zone of the transistor cell and above the first terminal zone of the edge cell. The method for fabricating these contact holes is chosen such that the contact holes reach through the complementary doped zones in the channel zone and the first terminal zone right into the channel zone and the first terminal zone. In the region of the edge cell, the cutout of the electrode layer acts as a mask for this etching process, which has the effect that the complementary doped region is removed as far as the edges of the cutout. In the region of the transistor cell, the regions of the complementary doped zone which are still covered by the further insulation layer remain during the fabrication of the contact hole.
With the inventive method, it is possible to dispense with additional method steps that prevent a doping of the first terminal zone of the edge cell during the method step for fabricating the source zones in the channel zones of the transistor cells. With the inventive method, the first terminal zone of the edge cell is doped together with the channel zones of the transistor cells. The resultant zone doped complementary with respect to the first terminal zone subsequently is removed during the fabrication of the contact holes. What is crucial here is that, in the region of the edge cell, the electrode layer that already serves as a mask during the doping step also serves as a mask during the etching process. In the region of the transistor cells, the further insulation layer protects regions of the complementary doped zones that serve as source zones, so that the regions are also still present in part after the fabrication of the contact holes. The fabrication of contact holes which reach through the source zones right into the channel zones of the transistor cells is necessary in order to short circuit the source zone and the channel zone by using a source electrode fabricated in the contact holes, in order largely to reduce parasitic bipolar effects and to obtain a freewheeling diode.
As explained, the patterned electrode layer forms the gate electrode of the component. Since this gate electrode is uncovered in the region of the edge cells, with the result that, after the deposition of a source electrode, there would be a short circuit present between the source electrode and the gate electrode, in one embodiment of the inventive method, the electrode layer is subdivided, during the patterning for fabricating the gate electrodes, into at least one first section in the region of the transistor cell and a second section in the region of the edge cell. This can be done, for example, by fabricating a cutout which reaches at least as far as the insulation layer. The cutout is filled by the further insulation layerxe2x80x94fabricated laterxe2x80x94and thus insulates regions of the electrode layer that form the gate electrodes from the region of the electrode layer in the region of the edge cell, which essentially serves as a mask there during the doping step and the etching step that is effected later.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a semiconductor component having at least one transistor cell and an edge cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.